我们收录了 "曾炜" 的 40 篇 paper：

• Distortion-characteristic estimation predistorter for high efficiency power amplifiers., 2020-05-12
• A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter., 2020-03-27
• A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs., 2020-03-11
• A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology., 2020-03-11
• A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System., 2020-03-11
• A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery., 2019-08-10
• A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking., 2019-01-07
• Fast analog layout prototyping for nanometer design migration., 2018-11-14
• An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming., 2018-11-14
• A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery., 2018-10-24
• A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS., 2018-03-09
• A 2.4 GHz reference-less wireless receiver for 1Mbps QPSK demodulation., 2017-05-26
• A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement., 2017-05-26
• Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications., 2017-05-26
• A 0.6 V, 1.66mW energy harvester and audio driver for tympanic membrane transducer with wirelessly optical signal and power transfer., 2017-05-26
• A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation., 2017-05-26
• A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery., 2017-05-26
• A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-μm CMOS Technology., 2017-05-26
• A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition., 2017-05-26
• Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor., 2017-05-26
• Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology., 2017-05-26
• A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression., 2017-05-26
• A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver., 2017-05-26
• A 40 Gbps optical receiver analog front-end in 65 nm CMOS., 2017-05-26
• A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications., 2017-05-26
• A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology., 2017-05-26
• Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology., 2017-05-26
• A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS., 2017-05-24
• A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery., 2017-05-24
• A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver., 2017-05-21
• A 10Bit, 10MS/s, low power cyclic ADC., 2017-05-21
• A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology., 2017-05-21
• Miniaturized 3-dimensional transformer design., 2017-05-17
• A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression., 2017-05-17
• A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector., 2017-05-17
• An 8 Gbps, 4: 1 transition-aware self-toggling multiplexer., 2017-05-17
• A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS., 2017-05-17
• A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector., 2017-05-17
• A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System., 2017-05-17
• A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector., 2017-05-17