Optimal bypass monitor for high performance last-level caches.
https://doi.org/10.1145/2370816.2370862
@inproceedings{DBLP:conf/IEEEpact/LiTXLC12,
author = {Lingda Li and
Dong Tong and
Zichao Xie and
Junlin Lu and
Xu Cheng},
editor = {Pen{-}Chung Yew and
Sangyeun Cho and
Luiz DeRose and
David J. Lilja},
title = {Optimal bypass monitor for high performance last-level caches},
booktitle = {International Conference on Parallel Architectures and Compilation
Techniques, {PACT} '12, Minneapolis, MN, {USA} - September 19 - 23,
2012},
pages = {315--324},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2370816.2370862},
doi = {10.1145/2370816.2370862},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/IEEEpact/LiTXLC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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