Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design.
https://doi.org/10.1109/ASAP.2019.000-8
@inproceedings{DBLP:conf/asap/WangL0ZHK19,
author = {Feng Wang and
Guojie Luo and
Guangyu Sun and
Jiaxi Zhang and
Peng Huang and
Jinfeng Kang},
title = {Parallel Stateful Logic in {RRAM:} Theoretical Analysis and Arithmetic
Design},
booktitle = {30th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2019, New York, NY, USA, July
15-17, 2019},
pages = {157--164},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ASAP.2019.000-8},
doi = {10.1109/ASAP.2019.000-8},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asap/WangL0ZHK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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