FPGA-based accelerator for long short-term memory recurrent neural networks.
https://doi.org/10.1109/ASPDAC.2017.7858394
@inproceedings{DBLP:conf/aspdac/GuanYSC17,
author = {Yijin Guan and
Zhihang Yuan and
Guangyu Sun and
Jason Cong},
title = {FPGA-based accelerator for long short-term memory recurrent neural
networks},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {629--634},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858394},
doi = {10.1109/ASPDAC.2017.7858394},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GuanYSC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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