A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints.
https://doi.org/10.1109/ASPDAC.2012.6165005
@inproceedings{DBLP:conf/aspdac/TsaiLH12,
author = {Shihheng Tsai and
Man{-}Yu Li and
Chung{-}Yang Huang},
title = {A semi-formal min-cost buffer insertion technique considering multi-mode
multi-corner timing constraints},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {505--510},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6165005},
doi = {10.1109/ASPDAC.2012.6165005},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/TsaiLH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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