SAT-controlled redundancy addition and removal: a novel circuit restructuring technique.
https://doi.org/10.1109/ASPDAC.2009.4796479
@inproceedings{DBLP:conf/aspdac/WuLHH09,
author = {Chi{-}An Wu and
Ting{-}Hao Lin and
Shao{-}Lun Huang and
Chung{-}Yang Huang},
editor = {Kazutoshi Wakabayashi},
title = {SAT-controlled redundancy addition and removal: a novel circuit restructuring
technique},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {191--196},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796479},
doi = {10.1109/ASPDAC.2009.4796479},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WuLHH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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