A false-path aware formal static timing analyzer considering simultaneous input transitions.
https://doi.org/10.1145/1629911.1629921
@inproceedings{DBLP:conf/dac/TsaiH09,
author = {Shihheng Tsai and
Chung{-}Yang Huang},
title = {A false-path aware formal static timing analyzer considering simultaneous
input transitions},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {25--30},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1629921},
doi = {10.1145/1629911.1629921},
timestamp = {Tue, 06 Nov 2018 16:58:15 +0100},
biburl = {https://dblp.org/rec/conf/dac/TsaiH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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