Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management.
https://doi.org/10.1145/3316781.3317875
@inproceedings{DBLP:conf/dac/Wei0C19,
author = {Xuechao Wei and
Yun Liang and
Jason Cong},
title = {Overcoming Data Transfer Bottlenecks in FPGA-based {DNN} Accelerators
via Layer Conscious Memory Management},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {125},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317875},
doi = {10.1145/3316781.3317875},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/dac/Wei0C19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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