Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs.
https://doi.org/10.1145/3061639.3062207
@inproceedings{DBLP:conf/dac/WeiYZCWHLC17,
author = {Xuechao Wei and
Cody Hao Yu and
Peng Zhang and
Youxiang Chen and
Yuxin Wang and
Han Hu and
Yun Liang and
Jason Cong},
title = {Automated Systolic Array Architecture Synthesis for High Throughput
{CNN} Inference on FPGAs},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {29:1--29:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062207},
doi = {10.1145/3061639.3062207},
timestamp = {Tue, 06 Nov 2018 16:58:15 +0100},
biburl = {https://dblp.org/rec/conf/dac/WeiYZCWHLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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