Design Space exploration of FPGA-based accelerators with multi-level parallelism.
https://doi.org/10.23919/DATE.2017.7927161
@inproceedings{DBLP:conf/date/ZhongPWLMN17,
author = {Guanwen Zhong and
Alok Prakash and
Siqi Wang and
Yun Liang and
Tulika Mitra and
Sma{\"{\i}}l Niar},
editor = {David Atienza and
Giorgio Di Natale},
title = {Design Space exploration of FPGA-based accelerators with multi-level
parallelism},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1141--1146},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927161},
doi = {10.23919/DATE.2017.7927161},
timestamp = {Fri, 27 Mar 2020 09:01:54 +0100},
biburl = {https://dblp.org/rec/conf/date/ZhongPWLMN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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