Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks.


https://doi.org/10.1145/2684746.2689060
@inproceedings{DBLP:conf/fpga/ZhangLSGXC15, author = {Chen Zhang and Peng Li and Guangyu Sun and Yijin Guan and Bingjun Xiao and Jason Cong}, editor = {George A. Constantinides and Deming Chen}, title = {Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks}, booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015}, pages = {161--170}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2684746.2689060}, doi = {10.1145/2684746.2689060}, timestamp = {Wed, 22 Jan 2020 14:30:11 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ZhangLSGXC15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }

本页面没有标签
本页面最近更新:2020/05/21更新历史
发现错误?想一起完善? 在 GitHub 上编辑此页!
本页面的全部内容在 CC BY-SA 4.0 SATA 协议之条款下提供,附加条款亦可能应用

Copyright © 2016 - 2020 PKU Scholar

最近更新: 52aade4, 2020-05-21