An analysis of ATPG and SAT algorithms for formal verification.
https://doi.org/10.1109/HLDVT.2001.972826
@inproceedings{DBLP:conf/hldvt/ParthasarathyHC01,
author = {Ganapathy Parthasarathy and
Chung{-}Yang Huang and
Kwang{-}Ting Cheng},
title = {An analysis of {ATPG} and {SAT} algorithms for formal verification},
booktitle = {Proceedings of the Sixth {IEEE} International High-Level Design Validation
and Test Workshop 2001, Monterey, California, USA, November 7-9, 2001},
pages = {177--182},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/HLDVT.2001.972826},
doi = {10.1109/HLDVT.2001.972826},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/hldvt/ParthasarathyHC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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