Improving inclusive cache performance with two-level eviction priority.
https://doi.org/10.1109/ICCD.2012.6378668
@inproceedings{DBLP:conf/iccd/LiTXLC12,
author = {Lingda Li and
Dong Tong and
Zichao Xie and
Junlin Lu and
Xu Cheng},
title = {Improving inclusive cache performance with two-level eviction priority},
booktitle = {30th International {IEEE} Conference on Computer Design, {ICCD} 2012,
Montreal, QC, Canada, September 30 - Oct. 3, 2012},
pages = {387--392},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ICCD.2012.6378668},
doi = {10.1109/ICCD.2012.6378668},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/iccd/LiTXLC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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