Efficient macroblock pipeline structure in high definition AVS video encoder VLSI architecture.
https://doi.org/10.1109/ISCAS.2010.5537498
@inproceedings{DBLP:conf/iscas/YinQJXG10,
author = {Hai Bing Yin and
Honggang Qi and
Huizhu Jia and
Don Xie and
Wen Gao},
title = {Efficient macroblock pipeline structure in high definition {AVS} video
encoder {VLSI} architecture},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {669--672},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537498},
doi = {10.1109/ISCAS.2010.5537498},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/YinQJXG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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