A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.
https://doi.org/10.1109/ISSCC.2019.8662494
@inproceedings{DBLP:conf/isscc/YangADXMWW19,
author = {Dihang Yang and
Asad A. Abidi and
Hooman Darabi and
Hao Xu and
David Murphy and
Hao Wu and
Zhaowen Wang},
title = {A Calibration-Free Triple-Loop Bang-Bang {PLL} Achieving 131fsrms
Jitter and-70dBc Fractional Spurs},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {266--268},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662494},
doi = {10.1109/ISSCC.2019.8662494},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YangADXMWW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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