Enabling coordinated register allocation and thread-level parallelism optimization for GPUs.
https://doi.org/10.1145/2830772.2830813
@inproceedings{DBLP:conf/micro/XieLLWSWF15,
author = {Xiaolong Xie and
Yun Liang and
Xiuhong Li and
Yudong Wu and
Guangyu Sun and
Tao Wang and
Dongrui Fan},
editor = {Milos Prvulovic},
title = {Enabling coordinated register allocation and thread-level parallelism
optimization for GPUs},
booktitle = {Proceedings of the 48th International Symposium on Microarchitecture,
{MICRO} 2015, Waikiki, HI, USA, December 5-9, 2015},
pages = {395--406},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2830772.2830813},
doi = {10.1145/2830772.2830813},
timestamp = {Mon, 16 Dec 2019 13:26:25 +0100},
biburl = {https://dblp.org/rec/conf/micro/XieLLWSWF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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