An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
https://doi.org/10.1109/NANOARCH.2015.7180576
@inproceedings{DBLP:conf/nanoarch/WuCWTSTZ15,
author = {Bi Wu and
Yuanqing Cheng and
Ying Wang and
Aida Todri{-}Sanial and
Guangyu Sun and
Lionel Torres and
Weisheng Zhao},
title = {An architecture-level cache simulation framework supporting advanced
{PMA} {STT-MRAM}},
booktitle = {Proceedings of the 2015 {IEEE/ACM} International Symposium on Nanoscale
Architectures, {NANOARCH} 2015, Boston, MA, USA, July 8-10, 2015},
pages = {7--12},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/NANOARCH.2015.7180576},
doi = {10.1109/NANOARCH.2015.7180576},
timestamp = {Fri, 27 Mar 2020 09:00:33 +0100},
biburl = {https://dblp.org/rec/conf/nanoarch/WuCWTSTZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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