Floorplanning challenges in early chip planning.
https://doi.org/10.1109/SOCC.2011.6085096
@inproceedings{DBLP:conf/socc/ShinDLALNH11,
author = {Jeonghee Shin and
John A. Darringer and
Guojie Luo and
Merav Aharoni and
Alexey Lvov and
Gi{-}Joon Nam and
Michael B. Healy},
title = {Floorplanning challenges in early chip planning},
booktitle = {{IEEE} 24th International SoC Conference, {SOCC} 2011, Taipei, Taiwan,
September 26-28, 2011},
pages = {388--393},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/SOCC.2011.6085096},
doi = {10.1109/SOCC.2011.6085096},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/ShinDLALNH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}