Parallel intra coding for HEVC on CPU plus GPU platform.

https://doi.org/10.1109/VCIP.2015.7457815

@inproceedings{DBLP:conf/vcip/MaLWZM15,
  author    = {Juncheng Ma and
               Falei Luo and
               Shanshe Wang and
               Nan Zhang and
               Siwei Ma},
  title     = {Parallel intra coding for {HEVC} on {CPU} plus {GPU} platform},
  booktitle = {2015 Visual Communications and Image Processing, {VCIP} 2015, Singapore,
               December 13-16, 2015},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {https://doi.org/10.1109/VCIP.2015.7457815},
  doi       = {10.1109/VCIP.2015.7457815},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/conf/vcip/MaLWZM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

作者们： Juncheng Ma Falei Luo Shanshe Wang Nan Zhang 0015 Siwei Ma

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