Constraint Driven Pin Mapping for Concurrent SOC Testing.
https://doi.org/10.1109/ASPDAC.2002.994971
@inproceedings{DBLP:conf/vlsid/HuangMTSZZCR02,
author = {Yu Huang and
Nilanjan Mukherjee and
Chien{-}Chung Tsai and
Omer Samman and
Yahya Zaidan and
Yanping Zhang and
Wu{-}Tung Cheng and
Sudhakar M. Reddy},
title = {Constraint Driven Pin Mapping for Concurrent {SOC} Testing},
booktitle = {Proceedings of the {ASPDAC} 2002 / {VLSI} Design 2002, CD-ROM, 7-11
January 2002, Bangalore, India},
pages = {511--516},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.994971},
doi = {10.1109/ASPDAC.2002.994971},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/HuangMTSZZCR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}