Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs.
https://doi.org/10.1631/FITEE.1601121
@article{DBLP:journals/jzusc/ZhongSWWLDDJ17,
author = {Yinghui Zhong and
Shu{-}xiang Sun and
Wen{-}bin Wong and
Haili Wang and
Xiao{-}Ming Liu and
Zhiyong Duan and
Peng Ding and
Zhi Jin},
title = {Two-step gate-recess process combining selective wet-etching and digital
wet-etching for InAlAs/InGaAs InP-based HEMTs},
journal = {Frontiers Inf. Technol. Electron. Eng.},
volume = {18},
number = {8},
pages = {1180--1185},
year = {2017},
url = {https://doi.org/10.1631/FITEE.1601121},
doi = {10.1631/FITEE.1601121},
timestamp = {Thu, 05 Mar 2020 17:10:25 +0100},
biburl = {https://dblp.org/rec/journals/jzusc/ZhongSWWLDDJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}