Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking.
https://doi.org/10.1109/43.913756
@article{DBLP:journals/tcad/HuanC01,
author = {Chung{-}Yang Huang and
Kwang{-}Ting Cheng},
title = {Using word-level {ATPG} and modular arithmetic constraint-solvingtechniques
for assertion property checking},
journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
volume = {20},
number = {3},
pages = {381--391},
year = {2001},
url = {https://doi.org/10.1109/43.913756},
doi = {10.1109/43.913756},
timestamp = {Sat, 20 May 2017 00:23:54 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuanC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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