Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures.
https://doi.org/10.1109/TCAD.2017.2681072
@article{DBLP:journals/tcad/LiangTZLHG17,
author = {Yun Liang and
Wai Teng Tang and
Ruizhe Zhao and
Mian Lu and
Huynh Phung Huynh and
Rick Siow Mong Goh},
title = {Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures},
journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
volume = {36},
number = {12},
pages = {2106--2119},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2017.2681072},
doi = {10.1109/TCAD.2017.2681072},
timestamp = {Thu, 14 Dec 2017 17:35:30 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiangTZLHG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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