A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter.
https://doi.org/10.1109/ASICON.2015.7517109
@inproceedings{DBLP:conf/asicon/ChenCR15,
author = {Hung{-}Kai Chen and
Wei{-}Zen Chen and
Zhiyuan Ren},
title = {A 0.4V 53dB {SNDR} 250 MS/s time-based {CT} {\(\Delta\)}{\(\Sigma\)}
analog to digital converter},
booktitle = {2015 {IEEE} 11th International Conference on ASIC, {ASICON} 2015,
Chengdu, China, November 3-6, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASICON.2015.7517109},
doi = {10.1109/ASICON.2015.7517109},
timestamp = {Fri, 27 Mar 2020 08:59:38 +0100},
biburl = {https://dblp.org/rec/conf/asicon/ChenCR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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