A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery.
https://doi.org/10.1109/ASSCC.2014.7008914
@inproceedings{DBLP:conf/asscc/HongC14,
author = {Zheng{-}Hao Hong and
Wei{-}Zen Chen},
title = {A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and
data recovery},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
Taiwan, November 10-12, 2014},
pages = {277--280},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASSCC.2014.7008914},
doi = {10.1109/ASSCC.2014.7008914},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/HongC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
本页面没有标签