A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.
https://doi.org/10.1109/CICC.2013.6658528
@inproceedings{DBLP:conf/cicc/LiuCCTLY13,
author = {Yao{-}Chia Liu and
Wei{-}Zen Chen and
Mao{-}Hsuan Chou and
Tsung{-}Hsien Tsai and
Yen{-}Wei Lee and
Min{-}Shueh Yuan},
title = {A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using
{\(\Delta\)}{\(\Sigma\)} noise-shaped phase detector},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658528},
doi = {10.1109/CICC.2013.6658528},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/LiuCCTLY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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