A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement.


https://doi.org/10.1109/ESSCIRC.2016.7598313
@inproceedings{DBLP:conf/esscirc/ChenK16, author = {Wei{-}Zen Chen and Po{-}I Kuo}, title = {A {\(\Delta\)}{\(\Sigma\)} {TDC} with sub-ps resolution for {PLL} built-in phase noise measurement}, booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016}, pages = {347--350}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ESSCIRC.2016.7598313}, doi = {10.1109/ESSCIRC.2016.7598313}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/esscirc/ChenK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }

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