A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS.
https://doi.org/10.1109/ISSCC.2009.4977322
@inproceedings{DBLP:conf/isscc/YangC09,
author = {Song{-}Yu Yang and
Wei{-}Zen Chen},
title = {A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable
digital loop filter in 90nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {90--91},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977322},
doi = {10.1109/ISSCC.2009.4977322},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YangC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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