A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology.
https://doi.org/10.1109/VLSIC.2012.6243765
@inproceedings{DBLP:conf/vlsic/ChenLWJYHLHLL12,
author = {Wei{-}Zen Chen and
Tai{-}You Lu and
Yan{-}Ting Wang and
Jhong{-}Ting Jian and
Yi{-}Hung Yang and
Guo{-}Wei Huang and
Wen{-}De Liu and
Chih{-}Hua Hsiao and
Shu{-}Yu Lin and
Jung Yen Liao},
title = {A 160-GHz receiver-based phase-locked loop in 65 nm {CMOS} technology},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {12--13},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243765},
doi = {10.1109/VLSIC.2012.6243765},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChenLWJYHLHLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}