A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver.
https://doi.org/10.1109/VLSIC.2015.7231347
@inproceedings{DBLP:conf/vlsic/HuangC15,
author = {Shih{-}Hao Huang and
Wei{-}Zen Chen},
title = {A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant {CMOS}
optical receiver},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
2015},
pages = {120},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSIC.2015.7231347},
doi = {10.1109/VLSIC.2015.7231347},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HuangC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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