A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery.
https://doi.org/10.1109/JSSC.2015.2475122
@article{DBLP:journals/jssc/HongLC15,
author = {Zheng{-}Hao Hong and
Yao{-}Chia Liu and
Wei{-}Zen Chen},
title = {A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap {DFE} Embedded Clock
and Data Recovery},
journal = {J. Solid-State Circuits},
volume = {50},
number = {11},
pages = {2625--2634},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2015.2475122},
doi = {10.1109/JSSC.2015.2475122},
timestamp = {Fri, 26 May 2017 22:54:57 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HongLC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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