A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology.
https://doi.org/10.1109/JSSC.2009.2039530
@article{DBLP:journals/jssc/YangCL10,
author = {Song{-}Yu Yang and
Wei{-}Zen Chen and
Tai{-}You Lu},
title = {A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically
Reconfigured Digital Loop Filter in 90 nm {CMOS} Technology},
journal = {J. Solid-State Circuits},
volume = {45},
number = {3},
pages = {578--586},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2009.2039530},
doi = {10.1109/JSSC.2009.2039530},
timestamp = {Fri, 26 May 2017 22:54:57 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YangCL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
本页面没有标签