Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology.
https://doi.org/10.1109/TCSI.2005.862068
@article{DBLP:journals/tcas/ChenL06,
author = {Wei{-}Zen Chen and
Chao{-}Hsin Lu},
title = {Design and anaylsis of a 2.5-Gbps optical receiver analog front-end
in a 0.35-{\(\mu\)}m digital {CMOS} technology},
journal = {{IEEE} Trans. on Circuits and Systems},
volume = {53-I},
number = {5},
pages = {977--983},
year = {2006},
url = {https://doi.org/10.1109/TCSI.2005.862068},
doi = {10.1109/TCSI.2005.862068},
timestamp = {Fri, 26 May 2017 22:51:20 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChenL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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